US 11,854,476 B1
Timing controller having mechanism for frame synchronization, display panel thereof, and display system thereof
Yao-Min Chou, Hsinchu (TW); and Kai-Wen Shao, Hsinchu (TW)
Assigned to Novatek Microelectronics Corp., Hsinchu (TW)
Filed by Novatek Microelectronics Corp., Hsinchu (TW)
Filed on Jun. 16, 2022, as Appl. No. 17/841,696.
Int. Cl. G09G 3/3208 (2016.01); G06T 1/20 (2006.01)
CPC G09G 3/3208 (2013.01) [G06T 1/20 (2013.01); G09G 2310/08 (2013.01); G09G 2360/02 (2013.01); G09G 2360/18 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a timing controller to transmit a first tearing (TE) signal to an application processor and receive a first image frame from the application processor after the application processor receives the first TE signal, and
a control circuit to generate a first sync signal when the timing controller receives the first image frame, wherein when the application processor receives a second TE signal and the application processor is not ready to transmit a second image frame to the timing controller, the control circuit delays a first waiting period to generate a second sync signal, wherein the timing controller further to transmit a third TE signal to the application processor and receive a third image frame from the application processor after the application processor receives the third TE signal, and
the control circuit further to generate a third sync signal when the timing controller receives the third image frame, wherein when the application processor receives a fourth TE signal, the control circuit further to generate a fourth sync signal, and a first interval between the first sync signal and the second sync signal is different from a second interval between the third sync signal and the fourth sync signal.