US 11,854,174 B2
Method and system of performing convolution in neural networks with variable dilation rate
Dinesh Kumar Yadav, Bangalore (IN); Ankur Deshwal, Bangalore (IN); Saptarsi Das, Bangalore (IN); Junwoo Jang, Suwon-si (KR); and Sehwan Lee, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jun. 28, 2022, as Appl. No. 17/851,704.
Application 17/851,704 is a continuation of application No. 16/733,314, filed on Jan. 3, 2020, granted, now 11,423,251.
Claims priority of application No. 201941000324 (IN), filed on Jan. 3, 2019; and application No. 201941000324 (IN), filed on Dec. 27, 2019.
Prior Publication US 2022/0374651 A1, Nov. 24, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06T 5/20 (2006.01); G06N 3/08 (2023.01); G06F 18/2111 (2023.01); G06T 1/00 (2006.01)
CPC G06T 5/20 (2013.01) [G06F 18/2111 (2023.01); G06N 3/08 (2013.01); G06T 1/0007 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A processor-implemented convolution method in a neural network, by a processor of a computing system, the method comprising:
receiving, by the processor, an input image including a plurality of pixel values;
receiving, by the processor, a size of a first kernel of another neural network and a dilation rate set for the first kernel;
generating, by the processor, one or more disintegrated kernels by disintegrating the first kernel into the one or more disintegrated kernels of the neural network;
generating, by the processor, one or more feature matrices of the neural network by performing a convolution operation between one or more kernel values of the one or more disintegrated kernels and pixel values corresponding to each block of one or more blocks of the input image; and
determining, by the processor, an output image based on a combination of the one or more feature matrices.