US 11,853,856 B2
Programming methods for neural network using non-volatile memory array
Farnood Merrikh Bayat, Goleta, CA (US); Xinjie Guo, Goleta, CA (US); Dmitri Strukov, Goleta, CA (US); Nhan Do, Saratoga, CA (US); Hieu Van Tran, San Jose, CA (US); Vipin Tiwari, Dublin, CA (US); and Mark Reiten, Alamo, CA (US)
Assigned to SILICON STORAGE TECHNOLOGY, INC., San Jose, CA (US)
Filed by Silicon Storage Technology, Inc., San Jose, CA (US); and The Regents of the University of California, Oakland, CA (US)
Filed on Jan. 18, 2020, as Appl. No. 16/746,852.
Application 16/746,852 is a continuation of application No. 15/594,439, filed on May 12, 2017, granted, now 11,308,383.
Claims priority of provisional application 62/337,760, filed on May 17, 2016.
Prior Publication US 2020/0151543 A1, May 14, 2020
Int. Cl. G11C 16/04 (2006.01); G06N 3/04 (2023.01); G06N 3/063 (2023.01); G11C 11/54 (2006.01); G11C 16/34 (2006.01); G11C 29/38 (2006.01); G06N 3/045 (2023.01); G11C 16/08 (2006.01); G11C 16/12 (2006.01); G11C 16/16 (2006.01); G06F 3/06 (2006.01)
CPC G06N 3/04 (2013.01) [G06F 3/061 (2013.01); G06F 3/0655 (2013.01); G06F 3/0688 (2013.01); G06N 3/045 (2023.01); G06N 3/063 (2013.01); G11C 11/54 (2013.01); G11C 16/08 (2013.01); G11C 16/12 (2013.01); G11C 16/16 (2013.01); G11C 16/3436 (2013.01); G11C 29/38 (2013.01)] 40 Claims
OG exemplary drawing
 
1. A method of programming a non-volatile memory cell in a neural network, the method comprising
determining a first read current of the non-volatile memory cell;
when the first read current is greater than a target current, performing a programming tuning process to increase the number of electrons on a floating gate of the non-volatile memory cell;
determining a second read current of the non-volatile memory cell; and
when the second read current is less than the target current, and not more than the target current minus a delta value, performing an erasing tuning process to decrease the number of electrons on the floating gate of the non-volatile memory cell.