US 11,853,765 B2
Processor authentication method
Michael Peeters, Tourinnes-la-Grosse (BE); and Fabrice Marinet, Chateauneuf le Rouge (FR)
Assigned to STMICROELECTRONICS (ROUSSET) SAS, Rousset (FR); and PROTON WORLD INTERNATIONAL N.V., Diegem (BE)
Filed by STMICROELECTRONICS (ROUSSET) SAS, Rousset (FR); and PROTON WORLD INTERNATIONAL N.V., Diegem (BE)
Filed on Apr. 14, 2022, as Appl. No. 17/721,193.
Application 17/721,193 is a continuation of application No. 16/833,012, filed on Mar. 27, 2020, granted, now 11,379,238.
Claims priority of application No. 1903346 (FR), filed on Mar. 29, 2019.
Prior Publication US 2022/0244961 A1, Aug. 4, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/30 (2018.01)
CPC G06F 9/30185 (2013.01) [G06F 9/30134 (2013.01); G06F 9/30145 (2013.01); G06F 9/30105 (2013.01)] 20 Claims
OG exemplary drawing
 
8. A processor, comprising:
a combination circuit that operates to combine a first instruction with signature data to generate a signed first instruction; and
an arithmetic and logic unit configured to process the signed first instruction to determine that the processor is authorized to process the first instruction;
wherein the signature data is a processing result of the arithmetic and logic unit processing a second instruction prior to the first instruction.