US 11,853,683 B2
Learning-based analyzer for mitigating latch-up in integrated circuits
Patrice M. Parris, Phoenix, AZ (US); David R. Gifford, Pflugerville, TX (US); and Bernd Lienhard, Austin, TX (US)
Assigned to Silicon Space Technology Corporation, Austin, TX (US)
Filed by Silicon Space Technology Corporation, Austin, TX (US)
Filed on Oct. 3, 2022, as Appl. No. 17/958,930.
Application 17/958,930 is a continuation of application No. 16/397,571, filed on Apr. 29, 2019, granted, now 11,461,531.
Prior Publication US 2023/0088804 A1, Mar. 23, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 30/398 (2020.01); G06N 5/046 (2023.01); G06N 20/00 (2019.01); G03F 1/42 (2012.01); G06F 119/08 (2020.01)
CPC G06F 30/398 (2020.01) [G06N 5/046 (2013.01); G06N 20/00 (2019.01); G03F 1/42 (2013.01); G06F 2119/08 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A method, implemented by a learning-based system comprising at least one processor, the method comprising:
obtaining latch-up data concerning an integrated circuit, wherein the integrated circuit comprises at least a first portion and a second portion;
training the learning-based system based on training data derived from the latch-up data and a first layout rule concerning a first spacing between the first portion and the second portion; and
generating a second layout rule concerning the first spacing between the first portion and the second portion, wherein the second layout rule is different from the first layout rule.