CPC G06F 30/398 (2020.01) [G06N 5/046 (2013.01); G06N 20/00 (2019.01); G03F 1/42 (2013.01); G06F 2119/08 (2020.01)] | 20 Claims |
1. A method, implemented by a learning-based system comprising at least one processor, the method comprising:
obtaining latch-up data concerning an integrated circuit, wherein the integrated circuit comprises at least a first portion and a second portion;
training the learning-based system based on training data derived from the latch-up data and a first layout rule concerning a first spacing between the first portion and the second portion; and
generating a second layout rule concerning the first spacing between the first portion and the second portion, wherein the second layout rule is different from the first layout rule.
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