US 11,853,609 B2
Power mode control in a multi-memory device based on queue length
Taeksang Song, San Jose, CA (US); Saira Samar Malik, Lafayette, IN (US); and Chinnakrishnan Ballapuram, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jan. 26, 2022, as Appl. No. 17/585,298.
Claims priority of provisional application 63/181,065, filed on Apr. 28, 2021.
Prior Publication US 2022/0350535 A1, Nov. 3, 2022
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0625 (2013.01); G06F 3/0656 (2013.01); G06F 3/0679 (2013.01)] 23 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a non-volatile memory;
a volatile memory configured to operate as a cache for the non-volatile memory; and
an interface controller coupled with the non-volatile memory and the volatile memory, the interface controller operable to cause the apparatus to:
determine whether a quantity of queued commands for the non-volatile memory is less than a threshold quantity, wherein the quantity of queued commands comprises commands pending for the non-volatile memory and commands issued to the non-volatile memory;
transition the non-volatile memory from a first power mode to a second power mode that consumes less power than the first power mode based at least in part on determining that the quantity of queued commands for the non-volatile memory is less than the threshold quantity;
receive a command, from a host device, that indicates a power mode for the volatile memory; and
maintain the power mode of the non-volatile memory irrespective of receiving the command that indicates the power mode for the volatile memory.