US 11,853,570 B2
Controller and memory system having the controller
Chan Young Oh, Gyeonggi-do (KR); and Hoe Seung Jung, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Jul. 6, 2021, as Appl. No. 17/368,458.
Claims priority of application No. 10-2021-0002205 (KR), filed on Jan. 7, 2021.
Prior Publication US 2022/0214807 A1, Jul. 7, 2022
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/064 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0655 (2013.01); G06F 3/0679 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A memory system comprising:
a memory device including first memory blocks, within which a single bit is to be programmed into a memory cell by using a single level cell (SLC) method, and second memory blocks, within which two or more bits are to be programmed into a memory cell by using a multi-level cell (MLC)-or-more method; and
a controller configured to program first data in the first memory blocks by using the SLC method and then migrate the first data from the first memory blocks into the second memory blocks by using the MLC-or-more method,
wherein the controller is further configured to:
read the first data from the first memory blocks when a read request for the first data is received from a host within a specific amount of time after the migration;
when the read request for the first data is received from the host after the specific amount of time after the migration and when a number of free blocks among the first memory blocks is greater than a reference number, read the first data from the first memory blocks; and
when the read request for the first data is received from the host after the specific amount of time after the migration and the number of the free blocks among the first memory blocks is smaller than the reference number, read the first data from the second memory blocks.