US 11,853,556 B2
Combining sets of memory blocks in a memory device
Steven Michael Kientz, Westminster, CO (US); Larry J. Koudele, Erie, CO (US); Shane Nowell, Boise, ID (US); Michael Sheperek, Longmont, CO (US); and Bruce A. Liikanen, Berthoud, CO (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jun. 6, 2022, as Appl. No. 17/832,842.
Application 17/832,842 is a continuation of application No. 17/103,441, filed on Nov. 24, 2020, granted, now 11,354,043.
Prior Publication US 2022/0300166 A1, Sep. 22, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01); G06F 11/30 (2006.01)
CPC G06F 3/0614 (2013.01) [G06F 3/064 (2013.01); G06F 3/0631 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 11/3037 (2013.01); G06F 11/3058 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device; and
a processing device, operatively coupled to the memory device, the processing device to:
identify a first temperature level of a first set of memory blocks associated with the memory device;
identify a second temperature level of a second set of memory blocks associated with the memory device;
determine that a condition is satisfied based on a comparison of the first temperature level, the second temperature level, and an adjustable threshold level; and
in response to the condition being satisfied, combine the first set of memory blocks and the second set of memory blocks to generate a combined set of memory blocks.