US 11,853,244 B2
Reconfigurable computer accelerator providing stream processor and dataflow processor
Karthikeyan Sankaralingam, Madison, WI (US); Anthony Nowatzki, Madison, WI (US); and Vinay Gangadhar, Madison, WI (US)
Assigned to Wisconsin Alumni Research Foundation, Madison, WI (US)
Filed by Wisconsin Alumni Research Foundation, Madison, WI (US)
Filed on Jan. 26, 2017, as Appl. No. 15/416,670.
Prior Publication US 2018/0210730 A1, Jul. 26, 2018
Int. Cl. G06F 9/38 (2018.01); G06F 15/78 (2006.01); G06F 13/40 (2006.01); G06F 13/16 (2006.01); G06F 9/30 (2018.01); G06F 9/448 (2018.01); G06F 15/76 (2006.01); G06F 9/345 (2018.01); G06F 15/82 (2006.01)
CPC G06F 13/4022 (2013.01) [G06F 9/30087 (2013.01); G06F 9/3455 (2013.01); G06F 9/3834 (2013.01); G06F 9/3877 (2013.01); G06F 9/4494 (2018.02); G06F 13/1689 (2013.01); G06F 15/76 (2013.01); G06F 15/7889 (2013.01); G06F 15/825 (2013.01)] 2 Claims
OG exemplary drawing
 
1. A data flow computer architecture comprising:
a dataflow processor providing set of functional units and programmable switches interconnecting the functional units between input ports receiving input values and output ports providing output values, the functional units providing programmable arithmetic functions and the interconnection providing paths from input ports through functional units to output ports determined by the switch programming;
a clock requiring synchronous movement of data among functional units and programmable switches by one step for each clock cycle, a step being from a functional unit to a switch or from a switch to a functional unit; and
a configuration store holding data configuring the interconnection of the functional units and the arithmetic functions of the functional units to execute a predetermined program in which data received at the input ports is clocked through the functional units and programmable switches to the output ports to implement a sequence of arithmetic functions on the data;
wherein the functional units operate so that calculations occur as soon as operands are available at the functional units and so that memories for storing operands at the functional units are not required, and wherein the configuration store defines paths of data through the dataflow processor ensuring corresponding operands arrive at the same time at each functional unit according to the program by adjusting the path of data through the dataflow processor without a need for additional buffer storage elements.