CPC G06F 13/4004 (2013.01) [B60R 16/02 (2013.01); G06F 13/42 (2013.01); H04L 12/40 (2013.01); H04L 2012/40273 (2013.01)] | 22 Claims |
1. A distributed driver that comprises:
a first set of transistors each configured to drive a first bus line;
a first set of delay elements configured to enable and disable the first set of transistors sequentially;
a second set of transistors each configured to drive a second bus line; and
a second set of delay elements configured to enable and disable the second set of transistors sequentially;
wherein a first node in the first set of delay elements is capacitively coupled to a corresponding second node in the second set of delay elements to synchronize signal transitions at the first and second nodes.
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