US 11,853,238 B2
Memory system
Kenji Sakaue, Yokohama (JP); Toshiyuki Furusawa, Tokyo (JP); and Shinya Takeda, Yokohama (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Sep. 13, 2022, as Appl. No. 17/943,798.
Application 17/943,798 is a continuation of application No. 17/158,134, filed on Jan. 26, 2021, granted, now 11,500,793.
Claims priority of application No. 2020-111105 (JP), filed on Jun. 29, 2020.
Prior Publication US 2023/0004506 A1, Jan. 5, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 13/16 (2006.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01); H01L 23/00 (2006.01)
CPC G06F 13/1668 (2013.01) [G06F 13/4022 (2013.01); G06F 13/4282 (2013.01); H01L 23/562 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 2225/0652 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06586 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory system comprising:
a first chip including a first surface, the first chip including:
a memory cell array, and
a first bonding pad on the first surface, the first bonding pad being electrically coupled to the memory cell array; and
a second chip including a second surface, the second surface facing the first surface of the first chip, the second chip including:
a memory controller configured to control access to the memory cell array, and
a second bonding pad on the second surface, the second bonding pad being directly bonded with the first bonding pad of the first chip to be electrically coupled thereto, the second bonding pad further being electrically coupled to the memory controller.