| CPC G06F 13/1668 (2013.01) [G06F 2213/16 (2013.01)] | 20 Claims |
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1. A system comprising:
a memory device;
an input/output (IO) instruction memory; and
a processing device, operatively coupled with the memory device via a signal communication bus, to perform operations comprising:
retrieving an IO instruction of a plurality of IO instructions from the IO instruction memory, the IO instruction comprising a first number of bits;
generating an IO vector based on the IO instruction, the IO vector comprising a second number of bits, wherein the second number of bits is greater than the first number of bits, and wherein the IO instruction comprises a number of fields to directly control respective states of a subset of the second number of bits of the IO vector; and
causing a plurality of IO signals, based on the IO vector, to be driven on the signal communication bus to the memory device, wherein the plurality of IO signals comprises a number of signals equal to the second number of bits of the IO vector.
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