| CPC G06F 12/1045 (2013.01) [G06F 12/0802 (2013.01); G06F 2212/60 (2013.01)] | 18 Claims |
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1. An apparatus comprising:
an address translation cache comprising a plurality of cache entries, each cache entry to store address translation data dependent on one or more page table entries of a multi-level page table structure in memory, wherein each page table entry of the multi-level page table structure is usable as at least one of:
a branch page table entry that specifies a table address of a next level page table; and
a leaf page table entry that specifies an output address for an address translation mapping for a corresponding region of address space; and
cache control circuitry responsive to a partial-address-translation-invalidation request to:
perform an invalidation lookup operation to identify whether a given cache entry of the address translation cache is a target cache entry to be invalidated, wherein the target cache entry comprises a cache entry for which the address translation data comprises partial address translation data indicative of an address of the next level page table specified by the table address of a target page table entry when used as the branch page table entry; and
trigger an invalidation of the given cache entry when the given cache entry is identified to be the target cache entry,
said partial-address-translation-invalidation request indicating that the given cache entry is permitted to be retained when the given cache entry provides full address translation data indicative of an address of the corresponding region of address space corresponding to the output address specified by the target page table entry when used as the leaf page table entry.
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