US 11,853,226 B2
Address translation cache with use of page size information to select an invalidation lookup mode, or use of leaf-and-intermediate exclusive range-specifying invalidation request, or use of invalidation request specifying single address and page size information
Andrew Brookfield Swaine, Sheffield (GB)
Assigned to Arm Limited, Cambridge (GB)
Appl. No. 16/624,430
Filed by ARM LIMITED, Cambridge (GB)
PCT Filed May 15, 2018, PCT No. PCT/GB2018/051314
§ 371(c)(1), (2) Date Dec. 19, 2019,
PCT Pub. No. WO2019/025748, PCT Pub. Date Feb. 7, 2019.
Claims priority of application No. 1712251 (GB), filed on Jul. 31, 2017.
Prior Publication US 2020/0218665 A1, Jul. 9, 2020
Int. Cl. G06F 12/00 (2006.01); G06F 12/1036 (2016.01); G06F 12/0864 (2016.01); G06F 12/0882 (2016.01); G06F 12/0891 (2016.01); G06F 12/1009 (2016.01)
CPC G06F 12/1036 (2013.01) [G06F 12/0864 (2013.01); G06F 12/0882 (2013.01); G06F 12/0891 (2013.01); G06F 12/1009 (2013.01); G06F 2212/651 (2013.01); G06F 2212/657 (2013.01)] 17 Claims
OG exemplary drawing
 
1. An apparatus comprising:
an address translation cache comprising a plurality of cache entries, each cache entry to store address translation data dependent on one or more page table entries of one or more page tables stored in a memory system; and
control circuitry responsive to an invalidation request specifying address information corresponding to at least one target page table entry, to perform an invalidation lookup operation to identify at least one target cache entry of the address translation cache for which the address translation data is dependent on said at least one target page table entry, and to trigger invalidation of the address translation data stored in said at least one target cache entry;
wherein the control circuitry is configured to select which of a plurality of invalidation lookup modes to use for the invalidation lookup operation in dependence on page size information indicative of a page size of said at least one target page table entry, the plurality of invalidation lookup modes corresponding to different ways of identifying said at least one target cache entry in dependence on the address information.