US 11,853,218 B2
Semi and cached TLP coalescing
Amir Segev, Meiter (IL); Amir Rozen, Rishon Lezion (IL); and Shay Benisty, Beer Sheva (IL)
Assigned to Western Digital Technologies, Inc., San Jose, CA (US)
Filed by Western Digital Technologies, Inc., San Jose, CA (US)
Filed on May 18, 2022, as Appl. No. 17/747,056.
Application 17/747,056 is a continuation in part of application No. 17/184,531, filed on Feb. 24, 2021.
Claims priority of provisional application 63/116,459, filed on Nov. 20, 2020.
Prior Publication US 2022/0276962 A1, Sep. 1, 2022
Int. Cl. G06F 12/00 (2006.01); G06F 12/0815 (2016.01); G06F 12/02 (2006.01); G06F 12/0882 (2016.01)
CPC G06F 12/0815 (2013.01) [G06F 12/0246 (2013.01); G06F 12/0882 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A data storage device, comprising:
a memory device; and
a controller coupled to the memory device, wherein the controller is configured to:
receive a command, wherein the command comprises a plurality of logical block addresses (LBAs);
determine that one or more LBAs of the plurality of LBAs are not aligned to a transfer layer packet (TLP) boundary;
determine whether the one or more LBAs that are not aligned to a TLP boundary has a head that is unaligned that matches a previously stored tail that is unaligned; and
merge and transfer the head that is unaligned with a previously stored tail that is unaligned when the head that is unaligned matches the previously stored tail that is unaligned.