US 11,853,215 B2
Memory controller, system including the same, and operating method of memory device for increasing a cache hit and reducing read latency using an integrated commad
Wonseb Jeong, Hwaseong-si (KR); Heehyun Nam, Seoul (KR); and Jeongho Lee, Gwacheon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Aug. 23, 2021, as Appl. No. 17/408,767.
Claims priority of application No. 10-2020-0158053 (KR), filed on Nov. 23, 2020.
Prior Publication US 2022/0164286 A1, May 26, 2022
Int. Cl. G06F 12/08 (2016.01); G06F 12/0806 (2016.01); G06F 12/02 (2006.01); G06F 12/0862 (2016.01)
CPC G06F 12/0806 (2013.01) [G06F 12/0253 (2013.01); G06F 12/0862 (2013.01); G06F 2212/1036 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a first interface circuit configured to communicate with a host processor;
a second interface circuit configured to communicate with a memory comprising a plurality of storage regions;
a cache memory comprising a plurality of cache lines configured to temporarily store data; and
a controller configured to receive an integrated command from the host processor, the integrated command comprising memory operation information and cache management information, configured to control the memory based on a first command that is instructed according to the memory operation information, and configured to control at least one of the plurality of cache lines based on the cache management information,
wherein the memory operation information of the integrated command corresponds to a read command for a first piece of data,
wherein the cache management information is generated by the host processor requesting to the controller of the device to perform at least one of a cache flush, a cache keep, or a prefetching, and
wherein the controller is further configured to:
(i) output the first piece of data based on the cache management information instructing the cache flush; and
(ii) in response to outputting the first piece of data to the host processor, perform the cache flush to clear a first cache line, which stores the first piece of data, among the plurality of cache lines based on the cache management information.