US 11,853,162 B2
Controller and storage device
Lui Sakai, Kanagawa (JP)
Assigned to SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
Appl. No. 17/777,915
Filed by SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
PCT Filed Nov. 5, 2020, PCT No. PCT/JP2020/041328
§ 371(c)(1), (2) Date May 18, 2022,
PCT Pub. No. WO2021/106514, PCT Pub. Date Jun. 3, 2021.
Claims priority of application No. 2019-215091 (JP), filed on Nov. 28, 2019.
Prior Publication US 2022/0405168 A1, Dec. 22, 2022
Int. Cl. G11C 29/00 (2006.01); G06F 11/10 (2006.01); G06F 11/07 (2006.01); G06F 13/40 (2006.01)
CPC G06F 11/1068 (2013.01) [G06F 11/0772 (2013.01); G06F 13/4068 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A controller, comprising:
a processing circuit configured to:
write each data fragment of a plurality of data fragments in one memory chip of a plurality of memory chips, wherein
each data fragment of the plurality of data fragments includes a part of data to be written, and
each memory chip of the plurality of memory chips has an error correction function; and
read the plurality of data fragments corresponding to data to be read from the plurality of memory chips;
a first encoder configured to encode the data to be written with an erasure correction code such that each data fragment of the plurality of data fragments includes a parity; and
a first decoder configured to perform erasure correction by use of a part of the plurality of data fragments corresponding to the data to be read according to a completion status of error correction on a corresponding part of the plurality of data fragments in each memory chip of the plurality of memory chips, wherein the completion status of the error correction is acquired via a signal line.