CPC G06F 11/0751 (2013.01) [G06F 11/0745 (2013.01); G06F 11/0787 (2013.01)] | 20 Claims |
1. A system-on-chip (SOC) comprising:
a system bus;
a plurality of modules connected to the system bus;
a processor configured to control the plurality of modules via the system bus;
an interrupt controller configured to transmit an interrupt signal to the processor;
error detection circuitry connected between the system bus and the interrupt controller, wherein the error detection circuitry is configured to monitor at least one register imbedded in at least one of the plurality of modules; and
a power management unit configured to provide power for a various component in the SOC;
wherein the at least one register is configured to be reset if the error detection circuitry transmits a signal to the interrupt controller; and
wherein the error detection circuitry is configured to control power supply to the interrupt controller, the system bus, or the plurality of modules by controlling the power management unit.
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