US 11,853,145 B2
Power source management system and power source management method for SRAM circuit, and FPGA chip
Lei Tian, Shenzhen (CN); and Yinghao Liao, Shenzhen (CN)
Assigned to SHENZHEN PANGO MICROSYSTEMS CO., LTD, Shenzhen (CN)
Filed by SHENZHEN PANGO MICROSYSTEMS CO., LTD, Shenzhen (CN)
Filed on Apr. 28, 2022, as Appl. No. 17/732,491.
Application 17/732,491 is a continuation of application No. PCT/CN2020/129082, filed on Nov. 16, 2020.
Claims priority of application No. 202010095846.3 (CN), filed on Feb. 14, 2020.
Prior Publication US 2022/0283626 A1, Sep. 8, 2022
Int. Cl. G06F 1/32 (2019.01); G06F 1/3234 (2019.01)
CPC G06F 1/3275 (2013.01) 20 Claims
OG exemplary drawing
 
1. A power management system for a static random access memory (SRAM) circuit, adapted for a field programmable gate array (FPGA) chip; the power management system comprising:
a power management circuit, configured to supply power to the SRAM circuit, wherein power supply voltages of the power management circuit comprise a core voltage and an analog input-output voltage, and the power management circuit comprises a power-on reset circuit configured to determine whether powering-on of the core voltage and the analog input-output voltage is completed; and
a power management controller and an oscillator, configured to control the power management circuit to power on the SRAM circuit after the power-on reset circuit determines that the powering-on of the core voltage and the analog input-output voltage is completed; and
wherein the power management controller and the oscillator are further configured to control the power management circuit to erase the SRAM circuit after the SRAM circuit is powered on.