CPC G06F 1/3275 (2013.01) | 20 Claims |
1. A power management system for a static random access memory (SRAM) circuit, adapted for a field programmable gate array (FPGA) chip; the power management system comprising:
a power management circuit, configured to supply power to the SRAM circuit, wherein power supply voltages of the power management circuit comprise a core voltage and an analog input-output voltage, and the power management circuit comprises a power-on reset circuit configured to determine whether powering-on of the core voltage and the analog input-output voltage is completed; and
a power management controller and an oscillator, configured to control the power management circuit to power on the SRAM circuit after the power-on reset circuit determines that the powering-on of the core voltage and the analog input-output voltage is completed; and
wherein the power management controller and the oscillator are further configured to control the power management circuit to erase the SRAM circuit after the SRAM circuit is powered on.
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