US 11,853,139 B2
Clock and data signal transmission in a master/slave PMIC system
Kiminobu Sato, Kyoto (JP)
Assigned to ROHM CO., LTD., Kyoto (JP)
Filed by ROHM Co., LTD., Kyoto (JP)
Filed on Jan. 6, 2021, as Appl. No. 17/142,424.
Claims priority of application No. 2020-001708 (JP), filed on Jan. 8, 2020.
Prior Publication US 2021/0208658 A1, Jul. 8, 2021
Int. Cl. G06F 1/3203 (2019.01); H04L 7/00 (2006.01); G06F 1/04 (2006.01); H02M 3/156 (2006.01); G06F 1/26 (2006.01); G06F 1/10 (2006.01)
CPC G06F 1/3203 (2013.01) [G06F 1/04 (2013.01); H02M 3/156 (2013.01); H04L 7/0008 (2013.01); G06F 1/10 (2013.01); G06F 1/26 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A semiconductor device system, comprising:
a first semiconductor device as a master, the first semiconductor device including a clock terminal configured to at least one of output or receive a first clock,
a data terminal configured to at least one of output or receive data in synchronization with the first clock,
wherein,
the synchronized data is output from the data terminal, and
the first clock is output from the clock terminal irrespective of whether or not data transfer of the synchronized data is being executed; and
a second semiconductor device having a configuration same as the first semiconductor device, as a slave, wherein
the first semiconductor device as the master outputs the first clock, and
the first clock is input to the second semiconductor device which is the slave.