US 11,852,924 B2
Active matrix substrate and a liquid crystal display
Takahiro Mori, Sakai (JP)
Assigned to SHARP KABUSHIKI KAISHA, Sakai (JP)
Filed by Sharp Kabushiki Kaisha, Osaka (JP)
Filed on Feb. 13, 2023, as Appl. No. 18/108,705.
Application 18/108,705 is a continuation of application No. 17/724,773, filed on Apr. 20, 2022, granted, now 11,598,992.
Application 17/724,773 is a continuation of application No. 17/098,685, filed on Nov. 16, 2020, granted, now 11,320,701, issued on May 3, 2022.
Application 17/098,685 is a continuation of application No. 14/397,897, granted, now 10,838,259, issued on Nov. 17, 2020, previously published as PCT/JP2013/063022, filed on May 9, 2013.
Claims priority of application No. 2012-112771 (JP), filed on May 16, 2012.
Prior Publication US 2023/0205019 A1, Jun. 29, 2023
Int. Cl. G02F 1/1339 (2006.01); G02F 1/1345 (2006.01); G11C 19/28 (2006.01); G02F 1/1335 (2006.01); G02F 1/1368 (2006.01); G09G 3/36 (2006.01); G02F 1/1333 (2006.01); G02F 1/1362 (2006.01)
CPC G02F 1/1339 (2013.01) [G02F 1/1345 (2013.01); G02F 1/1368 (2013.01); G02F 1/133345 (2013.01); G02F 1/133512 (2013.01); G02F 1/136213 (2013.01); G09G 3/3677 (2013.01); G11C 19/28 (2013.01); G11C 19/287 (2013.01); G09G 2300/0408 (2013.01); G09G 2310/0286 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An active matrix substrate comprising:
an insulating substrate including a first end;
a display region provided on the insulating substrate and including a plurality of gate lines extending in a first direction and a plurality of pixel transistors electrically connected to the plurality of gate lines; and
a shift register monolithically formed on the insulating substrate, the shift register being arranged in a region between the first end and the display region, wherein:
the shift register includes a plurality of unit circuits that are multistage-connected and a first wiring connected to the plurality of unit circuits,
the plurality of unit circuits include a first unit circuit and a second unit circuit,
the first unit circuit includes:
a clock terminal of the first unit circuit into which a clock signal is input,
an output terminal of the first unit circuit outputting an output signal,
a first transistor including a source electrode and a drain electrode, one of the source electrode and the drain electrode being connected to the clock terminal of the first unit circuit and another of the source electrode and the drain electrode being connected to the output terminal of the first unit circuit,
a second transistor connected to the first transistor and an output terminal of the second unit circuit, and
a first capacitor including a first terminal connected to a gate electrode of the first transistor and a second terminal connected to the output terminal of the first unit circuit,
the first wiring connected to the plurality of unit circuits supplies a first potential to turn off the pixel transistor or the first transistor to the plurality of unit circuits,
the first transistor and the first capacitor are arranged in a region between the first end and the first wiring,
the second transistor is arranged in a region between a part of the first capacitor and the first wiring.