US 11,852,525 B2
Ambient light sensor circuits with a delta-sigma analog to digital converter with a switch network
Ravi Kumar Adusumalli, Eindhoven (NL); Rahul Thottathil, Eindhoven (NL); Gowri Krishna Kanth Avalur, Eindhoven (NL); and Sudhakar Singamala, Eindhoven (NL)
Assigned to PAX WATER TECHNOLOGIES INC., Richmond, CA (US); and AMS INTERNATIONAL AG, Jona (CH)
Appl. No. 17/774,854
Filed by ams International AG, Jona (CH)
PCT Filed Dec. 18, 2020, PCT No. PCT/EP2020/087086
§ 371(c)(1), (2) Date May 5, 2022,
PCT Pub. No. WO2021/130124, PCT Pub. Date Jul. 1, 2021.
Claims priority of provisional application 62/953,664, filed on Dec. 26, 2019.
Prior Publication US 2022/0393697 A1, Dec. 8, 2022
Int. Cl. G01J 1/42 (2006.01); G01J 1/18 (2006.01); G01J 1/46 (2006.01); H03M 3/00 (2006.01); G01J 1/44 (2006.01)
CPC G01J 1/4204 (2013.01) [G01J 1/18 (2013.01); G01J 1/46 (2013.01); H03M 3/368 (2013.01); H03M 3/458 (2013.01); G01J 2001/446 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A sensor circuit comprising:
a sensor input;
a delta-sigma analogue to digital converter comprising:
a first integrator having a first summing junction at a first integrator input, wherein the sensor input is coupled to the first summing junction, a first feedback capacitor, and a first integrator output,
a comparator coupled to the first integrator output and configured to compare the first integrator output with a comparator reference to generate a comparator output,
a digital output coupled to the comparator output, and
a converter clock;
wherein the delta-sigma analogue to digital converter further comprises:
a first switched capacitor;
a common mode voltage source providing a common mode voltage;
a reference voltage source providing a reference voltage;
a first switch network configured to, in a first clock phase, connect the first switched capacitor to one of the common mode voltage and the reference voltage to charge the switched capacitor to either a sum of the common mode voltage and the reference voltage or a difference between the common mode voltage and the reference voltage, and in a second clock phase, connect the first switched capacitor to transfer charge from the first switched capacitor into the first summing junction;
a controller to control the first switch network responsive to the comparator output to selectively connect the first switched capacitor to one of the common mode voltage and the reference voltage in the first clock phase.