US 11,851,325 B2
Methods for wafer bonding
Chien-Wei Chang, Hsin-Chu (TW); Ya-Jen Sheuh, Hsin-Chu (TW); Ren-Dou Lee, Hsinchu (TW); Yi-Chih Chang, Hsin-Chu (TW); Yi-Hsun Chiu, Zhubei (TW); and Yuan-Hsin Chi, Taichung County (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Nov. 26, 2019, as Appl. No. 16/695,673.
Claims priority of provisional application 62/773,668, filed on Nov. 30, 2018.
Prior Publication US 2020/0172393 A1, Jun. 4, 2020
Int. Cl. B81C 1/00 (2006.01); H01L 21/3105 (2006.01); H01L 21/02 (2006.01); H01L 21/66 (2006.01)
CPC B81C 1/00238 (2013.01) [H01L 21/02274 (2013.01); H01L 21/31053 (2013.01); H01L 22/12 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for bonding a pair of semiconductor substrates, wherein the pair of semiconductor substrates comprises a first semiconductor substrate and a second semiconductor substrate, the method comprising:
processing the first semiconductor substrate before bonding, wherein the processing before bonding comprises:
predetermining a first target surface roughness value and a second target surface roughness value, wherein the second target surface roughness value is from 200% to 300% of the first target surface roughness value,
repeating a cycle of performing chemical vapor deposition (CVD) of a dielectric material to form a dielectric layer on a top surface of the first semiconductor substrate followed by chemical mechanical polishing (CMP) on the top surface of the first semiconductor substrate when a roughness of the top surface is larger than or equal to the second target surface roughness value,
performing an additional CVD of the dielectric material on the top surface of the dielectric layer when the roughness of the top surface is smaller than the second target surface roughness value and larger than or equal to the first target surface roughness value; and
bonding the pair of semiconductor substrates together when the roughness of the top surface is smaller than the first target surface roughness value, wherein the second semiconductor substrate is in direct contact with the top surface of the dielectric layer.