US 11,844,212 B2
Semiconductor memory devices
Kiseok Lee, Hwaseong-si (KR); Junsoo Kim, Seongnam-si (KR); Hui-Jung Kim, Seongnam-si (KR); Bong-Soo Kim, Yongin-si (KR); Satoru Yamada, Yongin-si (KR); Kyupil Lee, Seongnam-si (KR); Sunghee Han, Hwaseong-si (KR); HyeongSun Hong, Seongnam-si (KR); and Yoosang Hwang, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd.
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on May 19, 2022, as Appl. No. 17/748,261.
Application 17/748,261 is a continuation of application No. 17/000,857, filed on Aug. 24, 2020, granted, now 11,355,509.
Application 17/000,857 is a continuation of application No. 16/027,887, filed on Jul. 5, 2018, granted, now 10,784,272, issued on Sep. 22, 2020.
Claims priority of application No. 10-2017-0158278 (KR), filed on Nov. 24, 2017.
Prior Publication US 2022/0278121 A1, Sep. 1, 2022
Int. Cl. H10B 41/27 (2023.01); H01L 23/532 (2006.01); G11C 7/18 (2006.01); G11C 8/14 (2006.01); H10B 41/35 (2023.01); G11C 11/404 (2006.01); G11C 11/4097 (2006.01); H01L 49/02 (2006.01)
CPC H10B 41/27 (2023.02) [G11C 7/18 (2013.01); G11C 8/14 (2013.01); H01L 23/53295 (2013.01); H01L 28/60 (2013.01); H10B 41/35 (2023.02); G11C 11/404 (2013.01); G11C 11/4097 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for manufacturing a semiconductor memory device, the method comprising:
forming a plurality of semiconductor layers stacked on a substrate;
forming a vertical insulation pattern extending through one or more of the plurality of semiconductor layers and defining one or more semiconductor patterns from the plurality of semiconductor layers;
forming one or more recessions by selectively etching the one or more semiconductor patterns, respectively;
expanding the one or more recessions by partially etching the vertical insulation pattern;
forming at least one first electrode in the one or more recessions, respectively;
forming a dielectric layer on the at least one first electrode; and
forming a second electrode on the dielectric layer.