CPC H04N 25/75 (2023.01) [G05D 1/0246 (2013.01); H04N 25/616 (2023.01); H04N 25/65 (2023.01); H04N 25/79 (2023.01)] | 20 Claims |
1. An apparatus comprising:
a plurality of pixels;
a comparator configured to compare an output signal of each of the plurality of pixels with a reference signal; and
a counter of K bits (K is a natural number) configured to operate in parallel with operation of the comparator,
wherein the apparatus converts the output signal of each of the plurality of pixels into a digital signal using an output of the comparator and an output of the counter;
an addition unit configured to add a plurality of the digital signals,
wherein the addition unit includes a serial binary adder of M bits (M is a natural number less than K), and
wherein the serial binary adder of M bits is configured to perform addition processing and subtraction processing in a multiple sampling.
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