US 11,843,883 B2
Solid-state imaging device and electronic device
Masayuki Tachi, Kanagawa (JP); Kazuhito Kobayashi, Kanagawa (JP); Daisuke Yoshioka, Kanagawa (JP); Shiro Omori, Kanagawa (JP); Takeshi Kozasa, Fukuoka (JP); Kazuhide Fujita, Kanagawa (JP); Naoto Hayashida, Kanagawa (JP); and Shoyu Tanaka, Kanagawa (JP)
Assigned to Sony Semiconductor Solutions Corporation, Kanagawa (JP)
Appl. No. 17/619,348
Filed by Sony Semiconductor Solutions Corporation, Kanagawa (JP)
PCT Filed Jun. 18, 2020, PCT No. PCT/JP2020/023985
§ 371(c)(1), (2) Date Dec. 15, 2021,
PCT Pub. No. WO2020/262193, PCT Pub. Date Dec. 30, 2020.
Claims priority of application No. 2019-117530 (JP), filed on Jun. 25, 2019.
Prior Publication US 2022/0345651 A1, Oct. 27, 2022
Int. Cl. H04N 25/704 (2023.01); H04N 25/44 (2023.01); H04N 25/46 (2023.01); H04N 25/77 (2023.01); H04N 25/533 (2023.01); H04N 25/583 (2023.01)
CPC H04N 25/704 (2023.01) [H04N 25/44 (2023.01); H04N 25/46 (2023.01); H04N 25/533 (2023.01); H04N 25/583 (2023.01); H04N 25/77 (2023.01)] 20 Claims
OG exemplary drawing
 
1. A solid-state imaging device, comprising:
a pixel array unit in which a plurality of pixels is two-dimensionally arrayed,
wherein the plurality of pixels includes sets of phase difference pixels for phase difference detection, each of the sets including a respective first phase difference pixel and a respective second phase difference pixel adjacent to each other;
wherein the pixel array unit has an array pattern in which a plurality of pixel units, each of the pixel units including neighboring pixels of a same respective color, are regularly arrayed; and
wherein, in reading the plurality of pixels,
pixel signals of a first subset of the phase difference pixels are added in a first pattern of horizontal and vertical addition, and
pixel signals of a second subset of the phase difference pixels are discarded in a second pattern of the horizontal and vertical addition.