CPC H04L 67/148 (2013.01) [H04L 63/0853 (2013.01); H04L 63/0892 (2013.01); H04L 67/1097 (2013.01)] | 20 Claims |
1. An apparatus comprising at least one processor and at least one memory, the at least one memory having computer-coded instructions stored thereon that, in execution with the at least one processor, cause the apparatus to:
establish a plurality of connection channels associated with a plurality of user data objects, each user data object corresponding to a computing device of a plurality of computing devices,
wherein each of the plurality of connection channels provides access to functionality associated with a shared electronic data object via the computing device corresponding to the user data object;
determine, via interaction with the shared electronic data object, a set of user-driven actions to be performed in a defined order, wherein the set of user-driven actions comprises a first user-driven action to be performed via first functionality associated with a first user data object before a second user-driven action to be performed via second functionality associated with a second user data object based at least in part on the defined order;
detect a connection channel change associated with a first connection channel for a first computing device associated with the first user data object; and
in response to detection of the connection channel change, update the second functionality for a second connection channel associated with a second computing device corresponding to the second user data object, wherein the updated second functionality enables performance of the second user-driven action via the second connection channel associated with the second computing device,
wherein the second functionality is inaccessible before detecting the connection channel change.
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