| CPC H03K 5/1565 (2013.01) [G11C 11/4076 (2013.01); H03K 5/134 (2014.07)] | 20 Claims |
|
1. An apparatus comprising:
a first input node supplied with a first clock signal;
a first clock path configured to output a delayed first clock signal, the first clock path including first and second delay elements coupled in series;
a second clock path configured to output additional delayed first clock signal, the second clock path including third and fourth delay elements coupled in series;
a first mixer circuit configured to interpolate the delayed first clock signal and the additional delayed first clock signal to reproduce an adjusted clock signal as the first clock signal; and
a control circuit configured to control delay amounts of the first, second, third, and fourth delay elements with first, second, third, and fourth codes different from one another.
|