US 11,843,369 B2
Integrated MOS transistor with selective disabling of cells thereof
Davide Giuseppe Patti, Mascalucia (IT)
Assigned to STMicroelectronics S.r.l., Agrate Brianza (IT)
Filed by STMicroelectronics S.r.l., Agrate Brianza (IT)
Filed on Jul. 29, 2021, as Appl. No. 17/388,920.
Claims priority of application No. 102020000018733 (IT), filed on Jul. 31, 2020.
Prior Publication US 2022/0038094 A1, Feb. 3, 2022
Int. Cl. H01L 27/06 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H03K 17/30 (2006.01)
CPC H03K 17/302 (2013.01) [H01L 27/0629 (2013.01); H01L 29/0696 (2013.01); H01L 29/66734 (2013.01); H01L 29/7808 (2013.01); H01L 29/7813 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated device, comprising:
at least one MOS transistor integrated on a die of semiconductor material, the MOS transistor including:
a plurality of cells, each of the cells including:
a source region;
a gate element of electrical conductive material; and
a gate insulating layer of electrically insulating material insulating the gate element from the semiconductor material of the die;
a source contact coupled with the source regions; and
a gate contact coupled with the gate elements,
wherein one or more selected cells of the plurality of cells includes:
a disabling structure interposed between a coupled gate portion of the gate element coupled with the gate contact and an uncoupled gate portion of the gate element uncoupled from the gate contact, the disabling structure having an intervention voltage higher than a threshold voltage of the MOS transistor.