US 11,843,059 B2
Semiconductor device and electronic device
Shunpei Yamazaki, Tokyo (JP); Hajime Kimura, Kanagawa (JP); and Hitoshi Kunitake, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
Filed on Apr. 4, 2022, as Appl. No. 17/712,224.
Application 17/712,224 is a continuation of application No. 17/011,385, filed on Sep. 3, 2020, granted, now 11,335,812.
Claims priority of application No. 2019-199005 (JP), filed on Oct. 31, 2019; application No. 2019-203738 (JP), filed on Nov. 11, 2019; application No. 2019-208041 (JP), filed on Nov. 18, 2019; application No. 2019-216249 (JP), filed on Nov. 29, 2019; and application No. 2019-230250 (JP), filed on Dec. 20, 2019.
Prior Publication US 2022/0223739 A1, Jul. 14, 2022
Int. Cl. H01L 29/00 (2006.01); H01L 27/00 (2006.01); H01L 29/786 (2006.01); H10B 12/00 (2023.01); H01L 27/10 (2006.01); H10B 41/27 (2023.01); H10B 43/30 (2023.01)
CPC H01L 29/7869 (2013.01) [H01L 27/10 (2013.01); H10B 12/30 (2023.02); H10B 41/27 (2023.02); H10B 43/30 (2023.02)] 18 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a plurality of first openings arranged adjacent to each other,
a plurality of first transistors arranged adjacent to each other;
a plurality of second transistors over the plurality of first transistors;
a plurality of third transistors over the plurality of second transistors; and
a plurality of first capacitors, wherein one of the plurality of first capacitors surrounds one of the plurality of third transistors,
wherein one of the plurality of second transistors is filled in one of the plurality of first openings,
wherein one of the plurality of third transistors is filled in the one of plurality of first openings, and
wherein one of a source and a drain of one of the plurality of second transistors is electrically connected to a gate electrode of one of the plurality of third transistors and one electrode of one of the plurality of first capacitors.