US 11,843,045 B2
Power semiconductor device having overvoltage protection and method of manufacturing the same
Markus Beninger-Bina, Grosshelfendorf (DE); Thomas Basler, Ottenhofen (DE); Matteo Dainese, Villach (AT); and Hans-Joachim Schulze, Taufkirchen (DE)
Assigned to Infineon Technologies Austria AG, Villach (AT)
Filed by Infineon Technologies Austria AG, Villach (AT)
Filed on Aug. 28, 2020, as Appl. No. 17/005,642.
Application 17/005,642 is a division of application No. 16/402,712, filed on May 3, 2019, granted, now 10,790,384.
Application 16/402,712 is a continuation of application No. 15/926,131, filed on Mar. 20, 2018, granted, now 10,355,116, issued on Jul. 16, 2019.
Claims priority of application No. 102017105895 (DE), filed on Mar. 20, 2017; and application No. 102017118863 (DE), filed on Aug. 18, 2017.
Prior Publication US 2020/0395472 A1, Dec. 17, 2020
Int. Cl. H01L 29/739 (2006.01); H01L 29/04 (2006.01); H01L 29/66 (2006.01); H01L 27/07 (2006.01); H01L 29/08 (2006.01); H01L 29/423 (2006.01); H01L 29/808 (2006.01); H01L 29/32 (2006.01); H01L 27/02 (2006.01); H01L 29/861 (2006.01); H01L 29/10 (2006.01); H01L 29/36 (2006.01); H01L 29/74 (2006.01); H01L 29/16 (2006.01)
CPC H01L 29/7395 (2013.01) [H01L 27/0255 (2013.01); H01L 27/0727 (2013.01); H01L 29/04 (2013.01); H01L 29/083 (2013.01); H01L 29/1095 (2013.01); H01L 29/32 (2013.01); H01L 29/36 (2013.01); H01L 29/423 (2013.01); H01L 29/66348 (2013.01); H01L 29/7397 (2013.01); H01L 29/8083 (2013.01); H01L 29/861 (2013.01); H01L 29/0834 (2013.01); H01L 29/16 (2013.01); H01L 29/66325 (2013.01); H01L 29/7393 (2013.01); H01L 29/7398 (2013.01); H01L 29/7428 (2013.01); H01L 2924/13055 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of processing an overvoltage protection power semiconductor chip, comprising:
providing a semiconductor body to be coupled to a first load terminal and a second load terminal of the overvoltage protection power semiconductor chip, the first load terminal to be arranged at a frontside and the second load terminal to be arranged at a backside of the overvoltage protection power semiconductor chip, and wherein the semiconductor body comprises each of an active region and an inactive edge region that surrounds the active region,
forming, in the active region a plurality of breakthrough cells, each breakthrough cell comprising an insulation structure arranged at the frontside and having a recess into which the first load terminal is to extend and to interface with the semiconductor body;
forming a drift region having dopants of a first conductivity type;
forming an anode region having dopants of a second conductivity type, the anode region being electrically connected to the first load terminal and disposed in contact with the first load terminal;
forming a first barrier region having dopants of the second conductivity type at a lower dopant concentration than the anode region and arranged in contact with each of the anode region and the insulation structure, wherein the first barrier region forms a contiguous semiconductor layer throughout the plurality of breakthrough cells;
forming a second barrier region having dopants of the first conductivity type at a higher dopant concentration than the drift region and separating each of the anode region and at least a part of the first barrier region from the drift region; and
forming a doped contact region arranged in contact with the second load terminal, wherein the drift region is positioned between the second barrier region and the doped contact region.