| CPC H01L 29/42368 (2013.01) [H01L 29/41725 (2013.01); H01L 29/513 (2013.01)] | 20 Claims |
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1. A semiconductor device comprising:
a substrate;
a first gate insulating layer on the substrate;
second gate insulating layer arranged on the first gate insulating layer and including hafnium;
a gate electrode on the second gate insulating layer;
a gate capping pattern on the gate electrode;
a first gate spacer on a side surface of the gate electrode;
a second gate spacer on the first gate spacer;
a third gate spacer on the second gate spacer;
an interlayer insulating layer covering the third gate spacer; and
a contact plug in the interlayer insulating layer and electrically connected to the substrate,
wherein a width of the first gate insulating layer in a direction that is parallel to a top surface of the substrate is greater than a width of the second gate insulating layer in the direction,
the first gate spacer contacts a top surface of the first gate insulating layer and a side surface of the second gate insulating layer, and
the third gate spacer is spaced apart from the first gate insulating layer and the top surface of the substrate.
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