US 11,843,038 B2
Bipolar junction transistor with gate over terminals
Ming-Shuan Li, Zhudong Township (TW); Zi-Ang Su, Longtan Township (TW); and Ying-Keung Leung, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jan. 31, 2022, as Appl. No. 17/589,180.
Application 17/589,180 is a division of application No. 16/785,124, filed on Feb. 7, 2020, granted, now 11,239,330.
Prior Publication US 2022/0157953 A1, May 19, 2022
Int. Cl. H01L 29/417 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/73 (2006.01); H01L 29/423 (2006.01)
CPC H01L 29/41708 (2013.01) [H01L 29/42304 (2013.01); H01L 29/6681 (2013.01); H01L 29/66234 (2013.01); H01L 29/73 (2013.01); H01L 29/785 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
patterning a first doped well of a semiconductor substrate to form first fins, a second doped well of the semiconductor substrate to form second fins, and a third doped well of the semiconductor substrate to form third fins;
forming a gate structure over and along sidewalls of the first fins, the second fins, and the third fins; and
epitaxially growing a first epitaxy of a bipolar junction transistor (BJT) over the first fins on opposing sides of the gate structure, a second epitaxy of the BJT over the second fins on opposing sides of the gate structure, and a third epitaxy of the BJT over the third fins on opposing sides of the gate structure, the first epitaxy and the third conductivity having a first conductivity, the second epitaxy having a second epitaxy opposite the first conductivity, wherein the gate structure has a first portion, a second portion, and a third portion, the first portion, the second portion, and the third portion being electrically separated from each other, the first portion over the first fins, the second portion over the second fins, the third portion over the third fins.