US 11,843,037 B2
Semiconductor device and method of manufacturing the semiconductor device
Dukhyun Choe, Suwon-si (KR); Jinseong Heo, Seoul (KR); Yunseong Lee, Osan-si (KR); and Sanghyun Jo, Seoul (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Oct. 7, 2021, as Appl. No. 17/496,300.
Claims priority of application No. 10-2021-0036079 (KR), filed on Mar. 19, 2021; and application No. 10-2021-0040542 (KR), filed on Mar. 29, 2021.
Prior Publication US 2022/0302267 A1, Sep. 22, 2022
Int. Cl. H01L 29/40 (2006.01); H01L 29/78 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H10K 10/46 (2023.01)
CPC H01L 29/408 (2013.01) [H01L 29/4908 (2013.01); H01L 29/513 (2013.01); H01L 29/6684 (2013.01); H01L 29/7833 (2013.01); H01L 29/78391 (2014.09); H10K 10/474 (2023.02); H01L 29/516 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a substrate;
a channel layer at least one of on or in the substrate;
an insulation layer on the substrate;
a ferroelectric layer on the insulation layer;
a fixed charge layer on an interface between the insulation layer and the ferroelectric layer, the fixed charge layer including charges of a first polarity; and
a gate on the ferroelectric layer,
wherein the fixed charge layer is configured to have a charge density that generates a negative capacitance effect in response to the channel layer being in an inversion state, the fixed charge layer having a charge density greater than −5 μC/cm2 and less than 0, or a charge density greater than 0 and less than +5 μC/cm2.