US 11,843,001 B2
Devices including stacked nanosheet transistors
Byounghak Hong, Albany, NY (US); Seunghyun Song, Albany, NY (US); Ki-Il Kim, Clifton Park, NY (US); Gunho Jo, Clifton Park, NY (US); and Kang-Ill Seo, Albany, NY (US)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jul. 20, 2021, as Appl. No. 17/380,999.
Claims priority of provisional application 63/188,501, filed on May 14, 2021.
Prior Publication US 2022/0367520 A1, Nov. 17, 2022
Int. Cl. H04L 45/745 (2022.01); H04L 12/46 (2006.01); H04L 45/52 (2022.01); H01L 27/12 (2006.01); H01L 27/088 (2006.01); H01L 21/8234 (2006.01); H01L 21/822 (2006.01); H01L 21/84 (2006.01)
CPC H01L 27/1203 (2013.01) [H01L 21/8221 (2013.01); H01L 21/823412 (2013.01); H01L 21/823456 (2013.01); H01L 21/84 (2013.01); H01L 27/088 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A nanosheet transistor device comprising:
a transistor stack comprising:
a lower tri-gate nanosheet transistor having a first nanosheet width; and
an upper tri-gate nanosheet transistor on the lower tri-gate nanosheet transistor and having a second nanosheet width that is different from the first nanosheet width,
wherein the lower tri-gate nanosheet transistor comprises:
a pair of source/drain regions spaced apart from each other in a first direction;
at least one first nanosheet that is between the pair of source/drain regions and comprise four surfaces extending in the first direction; and
a lower gate in which three of the four surfaces of the at least one first nanosheet are located, wherein the lower gate does not overlay one of the four surfaces of the at least one first nanosheet viewed from a vantage point normal to the one of the four surfaces of the at least one first nanosheet, and wherein the upper tri-gate nanosheet transistor comprises:
at least one second nanosheet comprising four surfaces extending in the first direction; and
an upper gate, in which three of the four surfaces of the at least one second nanosheet are located, wherein the upper gate does not overlay one of the four surfaces of the at least one second nanosheet viewed from a vantage point normal to the one of the four surfaces of the at least one second nanosheet.