US 11,842,999 B2
Semiconductor device without a break region
Dae Seong Lee, Busan (KR); and Min Su Kim, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Feb. 8, 2022, as Appl. No. 17/666,872.
Application 17/666,872 is a division of application No. 16/733,634, filed on Jan. 3, 2020, granted, now 11,302,694.
Application 16/059,562 is a division of application No. 15/428,308, filed on Feb. 9, 2017, granted, now 10,062,697, issued on Aug. 28, 2018.
Application 16/733,634 is a continuation of application No. 16/059,562, filed on Aug. 9, 2018, granted, now 10,553,585, issued on Feb. 4, 2020.
Claims priority of provisional application 62/295,569, filed on Feb. 16, 2016.
Claims priority of application No. 10-2016-0049271 (KR), filed on Apr. 22, 2016.
Prior Publication US 2022/0165734 A1, May 26, 2022
Int. Cl. H01L 27/092 (2006.01); H01L 23/528 (2006.01); H01L 27/02 (2006.01); H01L 29/78 (2006.01); H03K 3/356 (2006.01); H03K 3/3562 (2006.01); H03K 19/0948 (2006.01); H03K 19/20 (2006.01); H01L 21/8238 (2006.01)
CPC H01L 27/0924 (2013.01) [H01L 23/528 (2013.01); H01L 27/0207 (2013.01); H01L 27/092 (2013.01); H01L 29/785 (2013.01); H03K 3/35625 (2013.01); H03K 3/356156 (2013.01); H03K 19/0948 (2013.01); H03K 19/20 (2013.01); H01L 21/823828 (2013.01); H01L 21/823871 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first inverter configured to receive a first signal, and generate a second signal by inverting the first signal; and
a second inverter configured to receive the second signal, and generate the first signal by inverting the second signal,
wherein the first inverter includes,
a first active fin extending in a first direction,
a second active fin spaced apart from the first active fin and extending in the first direction,
a third active fin extending in the first direction and being adjacent to the first active fin; and
a fourth active fin spaced apart from the third active fin and being adjacent to the second active fin and extending in the first direction,
a first gate line extending in a second direction, the second direction intersecting the first direction, the first gate line overlapping the first, second, third, and fourth active fins,
a second gate line extending in the second direction and spaced apart from the first gate line, the second gate line overlapping the first and second active fins,
a first metal line electrically connecting the first and second gate lines, the first metal line configured to provide the first signal to both the first gate line and the second gate line,
a second metal line electrically connected to a part of the first active fin between the first gate line and the second gate line and a part of the second active fin between the first gate line and the second gate line, the second metal line configured to transmit the second signal in response to the first signal, and
a third gate line disposed to overlap the first, the second, the third, and the fourth active fins, and spaced apart from the first gate line, the second gate line, and the first metal line.