US 11,842,985 B2
Semiconductor devices having through-stack interconnects for facilitating connectivity testing
Christian N. Mohr, Allen, TX (US); and Scott E. Smith, Plano, TX (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Oct. 13, 2022, as Appl. No. 17/965,561.
Application 16/894,568 is a division of application No. 16/020,140, filed on Jun. 27, 2018, granted, now 10,692,841, issued on Jun. 23, 2020.
Application 17/965,561 is a continuation of application No. 16/894,568, filed on Jun. 5, 2020, granted, now 11,495,577.
Prior Publication US 2023/0037349 A1, Feb. 9, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G01R 27/14 (2006.01); H01L 25/065 (2023.01); H01L 23/538 (2006.01)
CPC H01L 25/0657 (2013.01) [G01R 27/14 (2013.01); H01L 23/5385 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a stack of semiconductor dies including a first semiconductor die and a second semiconductor die stacked over the first semiconductor die, wherein the first semiconductor die includes a first detection circuit, wherein the second semiconductor die includes a second detection circuit, and wherein the stack has an edge;
interconnects extending between the first semiconductor die and the second semiconductor die, wherein the interconnects include—
a plurality of first interconnects, wherein the plurality of first interconnects are not connected to the first detection circuit or the second detection circuit;
a second interconnect positioned nearer to the edge than any of the plurality of first interconnects, wherein the second interconnect is connected to both the first detection circuit and the second detection circuit; and
wherein the first semiconductor die is configured to output an output signal indicative of a connectivity of the second interconnect.