US 11,842,983 B2
Semiconductor structure
Chen-Hua Yu, Hsinchu (TW); Chi-Hsi Wu, Hsinchu (TW); Der-Chyang Yeh, Hsinchu (TW); Hsien-Wei Chen, Hsinchu (TW); An-Jhih Su, Taoyuan County (TW); and Tien-Chung Yang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed on Nov. 12, 2021, as Appl. No. 17/525,641.
Application 17/525,641 is a division of application No. 16/714,176, filed on Dec. 13, 2019, granted, now 11,177,238.
Application 16/714,176 is a division of application No. 14/968,517, filed on Dec. 14, 2015, granted, now 10,510,715, issued on Dec. 17, 2019.
Prior Publication US 2022/0068880 A1, Mar. 3, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 25/065 (2023.01); H01L 25/00 (2006.01)
CPC H01L 25/0652 (2013.01) [H01L 25/50 (2013.01); H01L 2225/06562 (2013.01); H01L 2225/06582 (2013.01); H01L 2225/06593 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a plurality of first dies in a first level;
a plurality of second dies disposed in a second level over each of the first dies; and
a dielectric material surrounding the plurality of first dies and the plurality of second dies,
wherein each of the second dies in the second level overlaps a portion of each of the first dies in the first level.
 
6. A semiconductor structure, comprising:
a first die and a second die in a first level;
a third die and a fourth die in a second level over the first level; and
a dielectric material surrounding the first die, the second die, the third die and the fourth die,
wherein the third die overlaps a portion of the second die and exposes a first corner, a second corner and a third corner of the second die, and the fourth die overlaps a portion of the first die and exposes a first corner, a second corner and a third corner of the first die.
 
14. A semiconductor structure, comprising:
a first die and a second die in a first level;
a third die and a fourth die in a second level over the first level;
a dielectric material surrounding the first die, the second die, the third die and the fourth die,
wherein the third die overlaps a portion of the first die and a portion of the second die, and the fourth die overlaps another portion of the first die and another portion of the second die.