US 11,842,977 B2
Semiconductor package
Jooyoung Oh, Asan-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Aug. 26, 2021, as Appl. No. 17/446,074.
Claims priority of application No. 10-2020-0186781 (KR), filed on Dec. 29, 2020.
Prior Publication US 2022/0208717 A1, Jun. 30, 2022
Int. Cl. H01L 23/00 (2006.01); H01L 25/065 (2023.01); H01L 23/538 (2006.01)
CPC H01L 24/48 (2013.01) [H01L 23/5389 (2013.01); H01L 24/05 (2013.01); H01L 24/49 (2013.01); H01L 24/73 (2013.01); H01L 25/0657 (2013.01); H01L 2224/05552 (2013.01); H01L 2224/4809 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73265 (2013.01); H01L 2225/1035 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A semiconductor package comprising:
a package substrate which includes a substrate base and a plurality of wiring patterns, wherein the substrate base includes a chip-accommodating cavity, and wherein the plurality of wiring patterns include a plurality of bottom wiring patterns on a bottom surface of the substrate base and a plurality of top wiring patterns on a top surface of the substrate base;
a lower semiconductor chip which is disposed in the chip-accommodating cavity and is connected to the plurality of bottom wiring patterns through a plurality of lower bonding wires; and
an upper semiconductor chip, wherein the upper semiconductor chip includes:
a first portion which is attached to the lower semiconductor chip via an adhesive film directly contacting the upper semiconductor chip and the lower semiconductor chip, and
a second portion which overhangs the lower semiconductor chip,
wherein the upper semiconductor chip is attached across a top surface of the lower semiconductor chip and a topmost surface of the substrate base, and
wherein the top surface of the lower semiconductor chip is disposed at a same vertical level as the topmost surface of the substrate base.