US 11,842,968 B2
Power semiconductor device and substrate with dimple region
Kohei Yabuta, Tokyo (JP); Takayuki Yamada, Tokyo (JP); Yuya Muramatsu, Tokyo (JP); Noriyuki Besshi, Tokyo (JP); Yutaro Sugi, Tokyo (JP); Hiroaki Haruna, Tokyo (JP); Masaru Fuku, Tokyo (JP); and Atsuki Fujita, Tokyo (JP)
Assigned to MITSUBISHI ELECTRIC CORPORATION, Tokyo (JP)
Filed by MITSUBISHI ELECTRIC CORPORATION, Tokyo (JP)
Filed on Apr. 29, 2022, as Appl. No. 17/732,751.
Application 17/732,751 is a continuation of application No. 16/647,886, granted, now 11,342,281, previously published as PCT/JP2018/039659, filed on Oct. 25, 2018.
Claims priority of application No. 2017-209200 (JP), filed on Oct. 30, 2017.
Prior Publication US 2022/0254738 A1, Aug. 11, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/00 (2006.01); H01L 21/48 (2006.01); H01L 23/13 (2006.01)
CPC H01L 23/562 (2013.01) [H01L 21/4878 (2013.01); H01L 23/13 (2013.01); H01L 24/29 (2013.01); H01L 24/83 (2013.01); H01L 2224/29021 (2013.01); H01L 2224/29239 (2013.01); H01L 2224/29244 (2013.01); H01L 2224/29247 (2013.01); H01L 2224/29264 (2013.01); H01L 2224/29269 (2013.01); H01L 2224/8384 (2013.01); H01L 2924/1033 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/10272 (2013.01); H01L 2924/1203 (2013.01); H01L 2924/13055 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/35121 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A power semiconductor device, comprising:
a substrate; and
a semiconductor element bonded onto a first surface of the substrate through use of a sintered metal bonding material,
the substrate having, in the first surface, a first region immediately below a heat generation unit of the semiconductor element and a second region including a region located immediately below the semiconductor element in plan view and outside the first region and a region located outside an end portion of the semiconductor element, the second region having dimples.