US 11,842,967 B2
Semiconductor devices with backside power distribution network and frontside through silicon via
Kam-Tou Sio, Zhubei (TW); Cheng-Chi Chuang, New Taipei (TW); Chia-Tien Wu, Taichung (TW); Jiann-Tyng Tzeng, Hsin Chu (TW); Shih-Wei Peng, Hsinchu (TW); and Wei-Cheng Lin, Taichung (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on Oct. 25, 2021, as Appl. No. 17/452,188.
Application 17/452,188 is a division of application No. 16/656,715, filed on Oct. 18, 2019, granted, now 11,158,580.
Prior Publication US 2022/0045011 A1, Feb. 10, 2022
Int. Cl. H01L 23/495 (2006.01); H01L 23/538 (2006.01); H01L 23/00 (2006.01); H01L 21/48 (2006.01)
CPC H01L 23/5389 (2013.01) [H01L 21/486 (2013.01); H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 23/5383 (2013.01); H01L 23/5384 (2013.01); H01L 23/5386 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 2224/214 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a power distribution network in a backside dielectric layer, comprising:
a first conductive line in the backside dielectric layer; and
a second conductive line in the backside dielectric layer, wherein the backside dielectric layer is in contact with a first surface of a substrate;
a plurality of backside vias through the substrate and in contact with the first conductive line;
a via rail in contact with a second surface of the substrate, wherein the second surface is on an opposite side of the first surface;
a first interlayer dielectric in contact with the via rail and the substrate;
a second interlayer dielectric in contact with the first interlayer dielectric;
a first interconnect layer in the second interlayer dielectric;
a third interlayer dielectric in contact with the second interlayer dielectric;
a plurality of vias in the third interlayer dielectric, wherein the plurality of vias are electrically coupled to the via rail;
a top interconnect layer in the third interlayer dielectric; and
a power supply layer in contact with the third interlayer dielectric and the top interconnect layer.