US 11,842,947 B2
Fabricating field-effect transistors with interleaved source and drain finger configuration
Hailing Wang, Acton, MA (US); Dylan Charles Bartle, Arlington, MA (US); Hanching Fuh, Allston, MA (US); David Scott Whitefield, Andover, MA (US); and Paul T. DiCarlo, Marlborough, MA (US)
Assigned to SKYWORKS SOLUTIONS, INC., Irvine, CA (US)
Filed by SKYWORKS SOLUTIONS, INC., Irvine, CA (US)
Filed on May 11, 2021, as Appl. No. 17/317,737.
Application 17/317,737 is a continuation of application No. 16/566,837, filed on Sep. 10, 2019, granted, now 11,004,774.
Application 16/566,837 is a continuation of application No. 15/475,510, filed on Mar. 31, 2017, granted, now 10,410,957, issued on Sep. 10, 2019.
Claims priority of provisional application 62/316,518, filed on Mar. 31, 2016.
Claims priority of provisional application 62/316,519, filed on Mar. 31, 2016.
Prior Publication US 2021/0265242 A1, Aug. 26, 2021
Int. Cl. H01L 27/12 (2006.01); H01L 23/482 (2006.01); H01L 23/66 (2006.01); H01L 27/02 (2006.01); H01L 29/10 (2006.01); H01L 21/74 (2006.01); H01L 29/786 (2006.01); H01L 29/417 (2006.01); H04B 1/40 (2015.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01)
CPC H01L 23/482 (2013.01) [H01L 21/743 (2013.01); H01L 23/4824 (2013.01); H01L 23/4825 (2013.01); H01L 23/66 (2013.01); H01L 27/0203 (2013.01); H01L 27/0207 (2013.01); H01L 27/1203 (2013.01); H01L 29/1087 (2013.01); H01L 29/41733 (2013.01); H01L 29/78615 (2013.01); H01L 29/78654 (2013.01); H04B 1/40 (2013.01); H01L 21/82385 (2013.01); H01L 21/823456 (2013.01); H01L 2223/6677 (2013.01); H01L 2924/1421 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for fabricating a field-effect transistor (FET), the method comprising:
providing a substrate;
implementing a first assembly of source, gate, and drain on a first active region of the substrate;
implementing a second assembly of source, gate, and drain implemented on a second active region of the substrate;
implementing a third assembly of source, gate, and drain on a third active region of the substrate;
forming a first body contact between the first assembly and the second assembly, the first body contact formed such that application of a voltage on the first body contact influences operation of the first assembly and the second assembly;
forming a second body contact between the second assembly and the third assembly, the first assembly and the third assembly being dimensioned the same such that the first body contact and the second body contact are positioned symmetrically about a center line of the FET, the second assembly being dimensioned such that it has a width that is equal to the combined widths of the first assembly and the third assembly;
forming a finger configuration for the source, the gate, and the drain on each of the first assembly and the second assembly, each finger configuration including a plurality of fingers, the finger configuration of each of the first assembly and the second assembly resulting in source fingers and drain fingers being interleaved with the gate fingers, the source fingers and the drain fingers arranged in alternating rows; and
electrically connecting a particular source finger of the first assembly to a source finger of the second assembly that is positioned on the same row as the particular source finger of the first assembly.