US 11,842,942 B2
Structure and method related to a power module using a hybrid spacer
Liangbiao Chen, Scarborough, ME (US); Yong Liu, Cumberland Foreside, ME (US); Tzu-Hsuan Cheng, Scarborough, ME (US); Stephen St. Germain, Gilbert, AZ (US); and Roger Arbuthnot, Mesa, AZ (US)
Assigned to SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Phoenix, AZ (US)
Filed by SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Phoenix, AZ (US)
Filed on Mar. 18, 2022, as Appl. No. 17/655,398.
Application 17/655,398 is a continuation of application No. 16/784,999, filed on Feb. 7, 2020, granted, now 11,282,764.
Prior Publication US 2022/0208637 A1, Jun. 30, 2022
Int. Cl. H01L 23/367 (2006.01); H01L 23/373 (2006.01); H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H05K 7/20 (2006.01)
CPC H01L 23/3675 (2013.01) [H01L 21/565 (2013.01); H01L 23/3107 (2013.01); H01L 23/3735 (2013.01); H01L 24/32 (2013.01); H05K 7/2089 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/84801 (2013.01); H01L 2924/13055 (2013.01)] 21 Claims
OG exemplary drawing
 
21. A spacer block, comprising:
a solid spacer block;
an adjacent flexible spacer block;
a metal sheet, the solid spacer block and the adjacent flexible spacer block being attached to the metal sheet; and
a semiconductor device die coupled to a side of the spacer block, wherein the adjacent flexible spacer block is configured to accommodate mechanical displacement of the semiconductor device die induced by a coefficient of thermal expansion (CTE) mismatch.