US 11,842,901 B2
Semiconductor device, manufacturing method thereof, display device, and electronic device
Masami Jintyou, Tochigi (JP); Junichi Koezuka, Tochigi (JP); Takashi Hamochi, Tochigi (JP); and Yasuharu Hosaka, Tochigi (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
Filed on Jun. 17, 2022, as Appl. No. 17/843,083.
Application 17/843,083 is a continuation of application No. 17/064,730, filed on Oct. 7, 2020, granted, now 11,404,285.
Application 17/064,730 is a continuation of application No. 16/787,110, filed on Feb. 11, 2020, granted, now 10,886,143, issued on Jan. 5, 2021.
Application 16/787,110 is a continuation of application No. 16/270,624, filed on Feb. 8, 2019, granted, now 10,580,662, issued on Mar. 3, 2020.
Application 16/270,624 is a continuation of application No. 15/431,002, filed on Feb. 13, 2017, granted, now 10,204,798, issued on Feb. 12, 2019.
Claims priority of application No. 2016-028586 (JP), filed on Feb. 18, 2016; and application No. 2016-193217 (JP), filed on Sep. 30, 2016.
Prior Publication US 2022/0319866 A1, Oct. 6, 2022
Int. Cl. H01L 29/786 (2006.01); H01L 21/385 (2006.01); H01L 21/02 (2006.01); H01L 21/44 (2006.01); H01L 21/443 (2006.01); H01L 21/4757 (2006.01); H01L 29/04 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 29/51 (2006.01)
CPC H01L 21/385 (2013.01) [H01L 21/022 (2013.01); H01L 21/0214 (2013.01); H01L 21/0217 (2013.01); H01L 21/0234 (2013.01); H01L 21/02274 (2013.01); H01L 21/02323 (2013.01); H01L 21/02326 (2013.01); H01L 21/44 (2013.01); H01L 21/443 (2013.01); H01L 21/4757 (2013.01); H01L 29/045 (2013.01); H01L 29/4908 (2013.01); H01L 29/66969 (2013.01); H01L 29/7869 (2013.01); H01L 29/78648 (2013.01); H01L 29/518 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first gate electrode over a substrate;
a first insulating layer over the first gate electrode;
an oxide semiconductor layer over the first insulating layer, the oxide semiconductor layer having a single-layer structure;
a second insulating layer over the oxide semiconductor layer;
a third insulating layer over the second insulating layer;
a fourth insulating layer over the third insulating layer;
a second gate electrode comprising a first conductive film and a second conductive film over the first conductive film, the second gate electrode being over the second insulating layer; and
a third conductive film and a fourth conductive film over the fourth insulating layer,
wherein end portions of the first gate electrode extend beyond end portions of the second gate electrode,
wherein an end portion of the first conductive film is aligned with an end portion of the second conductive film,
wherein the third insulating layer is in contact with a top surface and a side surface of the second gate electrode and with a top surface of the second insulating layer,
wherein the fourth conductive film is electrically connected to the oxide semiconductor layer via an opening in the third insulating layer and the fourth insulating layer,
wherein the oxide semiconductor layer comprises a first region overlapping with the second gate electrode and a pair of second regions sandwiching the first region,
wherein a conductivity of the first region is different from a conductivity of the pair of second regions,
wherein a thickness of the second insulating layer is larger than a thickness of the first conductive film and smaller than a thickness of the second conductive film,
wherein a fifth conductive film formed by processing a film to be the first gate electrode is provided over the substrate, and
wherein the fifth conductive film is configured to function as an electrode of a capacitor.