US 11,842,778 B2
Memory system for performing cache program operation and operating method thereof
Jae Young Lee, Gyeonggi-do (KR); Yong Hwan Hong, Gyeonggi-do (KR); and Byung Ryul Kim, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Jul. 22, 2021, as Appl. No. 17/383,174.
Claims priority of application No. 10-2021-0025105 (KR), filed on Feb. 24, 2021.
Prior Publication US 2022/0270694 A1, Aug. 25, 2022
Int. Cl. G11C 16/34 (2006.01); G11C 16/10 (2006.01); G11C 7/10 (2006.01); G11C 29/44 (2006.01); G11C 16/26 (2006.01)
CPC G11C 16/3459 (2013.01) [G11C 7/1057 (2013.01); G11C 7/1063 (2013.01); G11C 16/102 (2013.01); G11C 16/26 (2013.01); G11C 29/4401 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a memory block including a plurality of pages;
a peripheral circuit configured to perform a first program operation for storing first page data in a first page among the plurality of pages and perform a second program operation for storing second page data in a second page among the plurality of pages after the first program operation;
a status register configured to store status information including information related to each of the first program operation and the second program operation;
a cache program operation controller configured to control the peripheral circuit to load the second page data from an external controller while the first program operation is performed; and
a status register controller configured to:
store, in the status register, first failure information indicating whether the first program operation passes or fails after the second program operation starts;
store, in the status register, a first value of validity information indicating that the first failure information is valid within a predetermined time period from when the second program operation starts; and
provide the external controller with the status information including the first failure information and the first value of the validity information which is stored in the status register,
wherein the status register controller is configured to provide the external controller with a second value of the validity information indicating that the first failure information is invalid, during a time period between when the second page data is loaded and when the first failure information is stored in the status register.