US 11,842,777 B2
Methods for reducing disturb errors by refreshing data alongside programming or erase operations
Raul Adrian Cernea, Santa Clara, CA (US)
Assigned to SUNRISE MEMORY CORPORATION, San Jose, CA (US)
Filed by SUNRISE MEMORY CORPORATION, San Jose, CA (US)
Filed on Nov. 12, 2021, as Appl. No. 17/525,712.
Claims priority of provisional application 63/114,958, filed on Nov. 17, 2020.
Prior Publication US 2022/0157391 A1, May 19, 2022
Int. Cl. G11C 16/34 (2006.01); G11C 16/26 (2006.01); G11C 16/14 (2006.01); G11C 16/04 (2006.01)
CPC G11C 16/3427 (2013.01) [G11C 16/0466 (2013.01); G11C 16/14 (2013.01); G11C 16/26 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A method ensuring data integrity in a plurality of memory pages, the memory pages being implemented in a 3-dimensional array of storage transistors, the method comprising:
dividing the memory pages into a predetermined number of refresh groups;
storing a value that represents a number of program or erase disturbs the memory pages have experienced, the value being stored in each of the memory pages;
and for each write operation to be performed on a selected one of the memory pages:
selecting one of the refresh groups;
reading data stored in storage transistors associated with the memory pages of the selected refresh group; and
concurrently (i) performing the write operation on the selected memory page, and (ii) writing the data read back into the storage transistors associated with the memory pages of the selected refresh group.