US 11,842,772 B2
Voltage bin boundary calibration at memory device power up
Michael Sheperek, Longmont, CO (US); Bruce A. Liikanen, Berthoud, CO (US); and Steve Kientz, Westminster, CO (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Jul. 5, 2022, as Appl. No. 17/857,942.
Application 17/857,942 is a continuation of application No. 17/022,908, filed on Sep. 16, 2020, granted, now 11,404,124.
Prior Publication US 2022/0336021 A1, Oct. 20, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/30 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); G11C 16/32 (2006.01); G06F 12/02 (2006.01); G06F 12/0882 (2016.01); G11C 16/34 (2006.01)
CPC G11C 16/10 (2013.01) [G06F 12/0246 (2013.01); G06F 12/0882 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01); G11C 16/32 (2013.01); G11C 16/3404 (2013.01); G06F 2212/7207 (2013.01); G11C 2207/2254 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
identifying a first bin boundary for a first voltage bin associated with a die of a memory device, the first bin boundary corresponding to a first block family associated with the first voltage bin;
determining a first bin boundary offset between the first block family and a second block family; and
updating the first bin boundary based on the first bin boundary offset.