| CPC G11C 11/418 (2013.01) [G11C 11/412 (2013.01); G11C 11/419 (2013.01)] | 8 Claims |
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1. A memory device, comprising:
a memory block, wherein each memory block comprises:
a plurality of memory cells, wherein a row of memory cells in the memory block are coupled to more than one word lines, and a column of memory cells in the memory block are coupled to a corresponding bit line and a corresponding multiplexer;
a row decode circuit, coupled to the plurality of memory blocks and comprising a plurality of a row decoders, wherein the plurality of row decoders are respectively allocated to the rows of memory cells in the plurality of memory blocks; and
a control circuit, coupled to the row decoder circuit and indicating which word line, bit line and multiplexer are enabled,
wherein the control circuit comprises:
a plurality of pre-decode circuits, wherein each pre-decode circuit generates a group of pre-decode signals and transmits the group of pre-decode signals to the row decode circuit; and
a column selection control circuit, generating a column selection signal based on an input signal of the column selection control circuit and a clock signal to select the multiplexer needed to be enabled,
wherein the input signal of the column selection control circuit is selected based on log2 i low bit address signals from memory address of the memory device, an address signal output by the control circuit is selected based on the input signal of the column selection control circuit, and an input signal of the pre-decode circuit is selected based on other (log2 M−log2 i) address signals from memory address of the memory device,
wherein i is an integer exponent of 2 and is regarded as the number of columns of memory cells of each memory block, and M is an integer exponent of 2 larger than and approaching the number of rows of the memory block,
wherein each row decoder comprises a plurality of sub decoders which are used to enable the different word lines, and each row decoder further comprises a sub decoder and a NOT gate which are used to enable the plurality of sub decoders used to enable the different word lines, wherein the sub decoder influences a state of two word lines and the NOT gate influences the state of only one of the two word lines,
wherein the number of the sub decoders used to enable the different word lines is the same as the number of the word lines configured for the row of memory cells.
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