US 11,842,705 B2
Display apparatus and electronic device
Susumu Kawashima, Atsugi (JP); Koji Kusunoki, Isehara (JP); Kazunori Watanabe, Machida (JP); and Naoto Kusumoto, Isehara (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Kanagawa-ken (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on Jun. 21, 2022, as Appl. No. 17/844,931.
Application 17/844,931 is a continuation of application No. 17/298,999, granted, now 11,373,610, previously published as PCT/IB2019/060823, filed on Dec. 16, 2019.
Claims priority of application No. 2018-242749 (JP), filed on Dec. 26, 2018.
Prior Publication US 2022/0319461 A1, Oct. 6, 2022
Int. Cl. G09G 3/34 (2006.01); G09G 3/36 (2006.01); G02F 1/1368 (2006.01)
CPC G09G 3/3648 (2013.01) [G02F 1/1368 (2013.01); G09G 3/3696 (2013.01); G09G 2300/0426 (2013.01); G09G 2330/021 (2013.01)] 5 Claims
OG exemplary drawing
 
1. A display apparatus comprising:
a first circuit configured to output first data;
a second circuit configured to generate second data by inverting the first data;
a third circuit configured to output third data;
a fourth circuit configured to generate fourth data by inverting the third data; and
a display region comprising a pixel,
wherein the first circuit is positioned on one end side of the display region,
wherein the third circuit is positioned on the other end side of the display region,
wherein the pixel comprises a first transistor, a second transistor, a third transistor, a first capacitor, and a fifth circuit which comprises a display device,
wherein one of a source and a drain of the first transistor is electrically connected to one electrode of the first capacitor and the third circuit,
wherein one of a source and a drain of the second transistor is electrically connected to one of a source and a drain of the third transistor and the other electrode of the first capacitor,
wherein the other of the source and the drain of the first transistor and the other of the source and the drain of the second transistor are electrically connected to at least one of the first circuit and the third circuit, and
wherein the other of the source and the drain of the third transistor is electrically connected to at least one of the second circuit and the fourth circuit.