US 11,842,697 B2
Electro-optical device having a storage capacitor formed by a data line and a potential line
Toshiyuki Kasai, Okaya (JP); and Takeshi Nomura, Shiojiri (JP)
Assigned to SEIKO EPSON CORPORATION, Tokyo (JP)
Filed by SEIKO EPSON CORPORATION, Tokyo (JP)
Filed on Apr. 27, 2023, as Appl. No. 18/140,261.
Application 18/140,261 is a continuation of application No. 17/962,039, filed on Oct. 7, 2022, granted, now 11,688,354.
Application 17/962,039 is a continuation of application No. 17/752,313, filed on May 24, 2022, granted, now 11,508,321, issued on Nov. 22, 2022.
Application 17/752,313 is a continuation of application No. 17/025,253, filed on Sep. 18, 2020, granted, now 11,355,072, issued on Jun. 7, 2022.
Application 17/025,253 is a continuation of application No. 16/585,983, filed on Sep. 27, 2019, granted, now 10,810,947, issued on Oct. 20, 2020.
Application 16/585,983 is a continuation of application No. 16/393,200, filed on Apr. 24, 2019, granted, now 10,453,400, issued on Oct. 22, 2019.
Application 16/393,200 is a continuation of application No. 15/959,765, filed on Apr. 23, 2018, granted, now 10,311,800, issued on Jun. 4, 2019.
Application 15/959,765 is a continuation of application No. 13/669,897, filed on Nov. 6, 2012, granted, now 9,984,630, issued on May 29, 2018.
Claims priority of application No. 2011-250386 (JP), filed on Nov. 16, 2011.
Prior Publication US 2023/0260467 A1, Aug. 17, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G09G 3/3233 (2016.01); G09G 3/3291 (2016.01)
CPC G09G 3/3291 (2013.01) [G09G 3/3233 (2013.01); G09G 2300/0814 (2013.01); G09G 2300/0838 (2013.01); G09G 2300/0861 (2013.01); G09G 2300/0876 (2013.01); G09G 2310/0256 (2013.01); G09G 2310/0275 (2013.01); G09G 2310/0289 (2013.01); G09G 2310/0297 (2013.01); G09G 2320/045 (2013.01)] 23 Claims
OG exemplary drawing
 
1. An electro-optical device comprising:
a first line configured to provide a first signal;
a data line extending in a first direction;
a potential line extending in the first direction;
a first capacitor being formed by the data line and the potential line, the first capacitor having a first end
formed by at least a portion of the potential line and a second end formed by at least a portion of the data line, wherein the portion of the potential line and the portion of the data line are adjacent in plan view; and
a pixel circuit including:
a driving transistor having a gate, a source, and a drain, the driving transistor being configured to control a current level according to a voltage between the gate and the source;
a writing transistor electrically connected between the data line and the gate of the driving transistor;
a second capacitor having one end electrically connected to the gate of the driving transistor;
a light-emitting element configured to emit light at a luminance according to the current level during a light-emitting period; and
an initialization transistor configured to be on during an initialization period different from the light-emitting period, to control an electrical connection between the potential line and the light-emitting element, wherein the first line is configured to provide the first signal to the initialization transistor, and wherein the light-emitting element does not emit light during the initialization period.